View TQ9501_64066.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

T
R
I
Q
U
I
N
T
S E M I C O N D U C T O R, I N C .
Data Data 32 Parity 4 Control 11 HOST Data 32 Parity 4 Control 12 Data 10 Control 2 TQ9502 Receiver 2 Optical Rx or Copper Interface 2 TQ9303 ENDEC 2 Fiber Optic Cable 10 Control 2 TQ9501 Transmitter 2 Optical Tx or Copper Interface 2
TQ9501/9502
531/1063 Mbaud Fibre Channel Transmitter and Receiver
TriQuint's Fibre Channel transmitter (TQ9501) and receiver (TQ9502) are part of the FC531/FC1063 (Fibre Channel 531 and 1063 Megabaud) chip set. In addition to the transmitter and receiver, TriQuint offers the ENcoder/ DECoder (TQ9303 ENDEC). The TQ9501, TQ9502, TQ9303 and a gigabit fiber optic module set provide a complete solution for Fibre Channel's FC0 and FC1 layers as well as partial support for the FC2 layer. The TQ9501 and TQ9502 are designed in TriQuint's proprietary 0.7-micron GaAs process, enabling the transmitter and receiver to run at higher speeds and lower power than with conventional processes. The transmitter and receiver data interface has been selected to be 10 bits in order to conserve input/output power and to reduce pin count and package size. The transmitter performs the parallel-to-serial conversion and generates the internal high-speed clock for the serial output. The receiver performs serial-toparallel conversion, recovers the clock and data from the serial input, and detects the K28.5 character (Fibre Channel standard "SYNC" transmission character). The TQ9303 ENDEC implements 8b/10b encoding and decoding, ordered set encoding and decoding, parity checking and generation, 32-bit CRC checking and generation, and word synchronization as defined in the Fibre Channel Physical and Signaling Interface Standard (FC-PH). Fibre Channel provides a high-speed physical layer for Intelligent Peripheral Interface (IPI) and Small Computer System Interface (SCSI) upper-layer command sets, High-Performance Parallel Interface (HIPPI) data link layer, and other user-defined command sets. Fibre Channel replaces the SCSI, IPI and HIPPI physical interfaces with a higherspeed interface capable of driving longer distances.
Features
* Compliant with ANSI X3T11 Fibre Channel Standard * Operates at 531.125 Mbaud and 1.0625 Gigabaud (1.25 Gigabaud max) * Low power dissipation (2.25 W, typical) * Low jitter * No external PLL components * 10-bit TTL-compatible data bus * Synchronous Data Bus Interface * Direct interface to TQ9303 ENDEC * Single +5 V supply * 48-pin MQuad package
DATACOM PRODUCTS
For additional information and latest specifications, see our website: www.triquint.com
1
TQ9501/TQ9502
Fibre Channel is optimized for predictable transfers of large blocks of data, such as those used in file transfers between processors (super computer, mainframe, super-mini, etc.), storage systems (disk and tape), and output-only devices such as laser printers and raster scan graphics terminals. The Fibre Channel protocol is implemented in hardware, making it simple, efficient and robust. The lower-level physical interface is decoupled from the higher-level protocol allowing the Fibre Channel to be configured with various topologies, including point-topoint, multi-drop bus, ring, and cross point switch. Fibre Channel supports distances up to 10 Km at baud rates of 132.8125 Mbaud to 1.0625 Gbaud. Copper media such as Coax and STP (Shielded Twisted Pair) are used for shorter distances while fiber optic cables are used for longer distances. Applications for the TQ9501 and TQ9502 include serial SCSI, IPI, HIPPI, point-to-point serial communication, ATM and other networking applications.
TriQuint offers two chip sets for Fibre Channel: the TQ9501 and TQ9502 chip set for 531.125 Mbaud and 1.0625 Gbaud, and the GA9101 and GA9102 chip set for the 265.625 Mbaud rate.
Functional Description - TQ9501 Transmitter
The TQ9501 serializes a 10-bit TTL input into a differential PECL output. The TQ9501 is composed of an input register, a parallel-to-serial converter, a PLL clock generator, a differential output buffer and a PECLto-TTL translator, as illustrated in Figure 1. The self-contained PLL (Phase-Locked Loop) clock generator requires no external components. It generates an internal high-speed bit clock for the serial output, an internal byte clock for the parallel-to-serial converter and BYTECLK, based on REFCLK (REFerence CLocK). BYTECLK is used by the TQ9303 ENDEC to generate TXCLK. TXD0..9 are latched into the input register on the rising edge of TXCLK. The parallel-to-serial converter serializes the data into a differential PECL buffer. TXD9 is sent first and TXD0 is sent last.
Figure 1. TQ9501 Transmitter
RATESEL REFCLK (25-31.25 MHz BYTECLK (50-62.5 MHz or 100-125 MH
LOOPEN TLX
PLL Clock Generator
TLY
Bit Clock
Byte Clock
TX
Parallelto-Serial Converter
Register
10
10
TXD0..9
TY SIG SIGN 2 PECL-to-TTL Converter
TXCLK SIGDET
2
For additional information and latest specifications, see our website: www.triquint.com
TQ9501/TQ9502
Figure 2. TQ9502 - Receiver
SYNCEN RX, RY RLX, RLY 2 2 Data Clock/Data Recovery (500-625 MBaud Clock or 1.0-1.25 GBaud) Serial-toParallel Converter
Register
Mux
2
10
10
RXD0..9
SYNC LOOPEN RATESEL REFCLK (25-31.25 MHz) X 40 RX Clock Generate RXCLK (50-62.5 MHz or 100-125 MH CLKPOL
The LOOPEN (LOOP ENable) pin selects between the two differential output pairs, TLX and TLY, or TX and TY. LOOPEN = 1 selects the differential output TLX and TLY, setting TX = 0 and TY = 1. Conversely, LOOPEN = 0 selects TX and TY, setting TLX = 0 and TLY = 1. This relationship is shown in Table 1.
The PECL-to-TTL translator block is a differential PECLto-TTL translator. It is normally used for translating PECL signals generated by optical receivers to TTL signals to drive control circuitry.
Table 1. LOOPEN Configuration
LOOPEN
0 1
Rx Input
RX, RY RLX, RLY
Tx Output
TX,TY TLX, TLY
For additional information and latest specifications, see our website: www.triquint.com
3
DATACOM PRODUCTS
TQ9501/TQ9502
Functional Description - TQ9502 Receiver
The TQ9502 consists of a clock and data recovery circuit, a multiplexer, and a serial-to-parallel converter block, as shown in Figure 3. The multiplexer selects between the RX and RY inputs or the RLX and RLY inputs. Outputs RTX, RTY, RLTX and RLTY, not shown on Figure 3, are provided for Fly-ByTM termination, which allows termination resistors to be placed away from the chip. The multiplexer output is selected by the LOOPEN pin as shown in Table 1. The selected data goes to the CDR (Clock/Data Recovery) block. The clock and data recovery block has two modes: clock recovery and frequency acquisition. In the clock input, it automatically switches to the frequency acquisition mode which causes the CDR to lock onto the REFCLK signal. This prevents the PLL from drifting away from the serial data rate and ensures that the CDR will properly lock onto the input serial data when it is reapplied. The receiver synchronizes 1 ms after applying power, REFCLK and data. The receiver synchronizes 200 s after applying valid data if power and REFCLK has already been applied. The output of this block is latched into the output register. When SYNCEN is high (SYNCronization ENable), the serial-to-parallel converter monitors the serial data for the K28.5 character. When it sees a K28.5, it realigns the 10-bit register to the K28.5 character and drives SYNC high. The clock generate block also detects SYNC going high, and delays the phase of the output RXCLK to coincide with the new alignment. Some bits may be lost during the realignment. When SYNCEN is low, SYNC is driven low and the serial-to-parallel converter ignores the K28.5 character. The output register takes in the 10-bit-wide output from the Serial-to-Parallel Converter and drives the RXD0..9 outputs. RXD0..9 are strobed on the rising edge of RXCLK. CLKPOL = 1 results in a longer setup time and shorter hold time than CLKPOL = 0. The first serial bit is placed in RXD9 and the tenth bit is placed in RXD0. Fibre Channel Interface Figure 3 illustrates a typical Fibre Channel physical layer block diagram using the TQ9501, TQ9502 and TQ9303 chip set. The interface between the host and ENDEC operates at 26.5625 MHz with a data width of 32-bits for the transmit path and a separate 32-bits for the receive path. The ENDEC performs the 8b/10b encoding and decoding; ordered set encoding and decoding; parity checking and generation; 32-bit CRC checking and generation; and word synchronization. The interface between the TQ9303 and the TQ9501/ TQ9502 operates at 531.25 or 106.250 MHz with an encoded data width of 10-bits. The serial interface operates from 531.125 Mbaud or 1.0625 Gbaud respectively, which is connected to an optical, coaxial or twisted pair interface. For additional information on the ENDEC, please refer to the TQ9303 data sheet.
4
For additional information and latest specifications, see our website: www.triquint.com
TQ9501/TQ9502
Figure 3. System Block Diagram - Fibre Channel
TQ9501 TX
SIGDET
Host TQ9303 ENDEC
RATESEL REFCLK LOOPEN
BTXD0..9 TXD0..9 CTXD0..31 TXCLK CTXC0,1 BTXCKOUT CTXP0..3 BYTECLK BTXCKIN CTXRAWA,B CTXRAW CTXPENN SIG, SIGN CTXPMODE CTXPERR RATESEL CTXCERR CTXCLK REFCLK CTXWREF LOOPEN RESETN CRXD0..31 CRXP0..3 BRXD0..9 CRXS0..5 BRXCLK RAWRX RXPMODE BRXSYNC WRDSYNCN RXCKPH0,1 CRXCLK
TX, TY TLX, TLY
Optical, Coaxial, or Twisted Pair Interface
Out
RXD0..9 RXCLK SYNC
RLX, RLY RX, RY 2 2 RTX RTY
Termination Network
SYNCEN CLKPOL
RLTX RLTY
TQ9303
...
Note that the fast edge rates of the TQ9303 TX bus outputs can affect the stability of the TQ9501 PLL. These edge rates can be effectively "slowed" by adding some series resistance of from 90 to 250 ohms to the TX data bus lines (TXD0..9) as shown in Figure 4. Resistance should also be added to TXCLK to maintain the correct timing relationship with the data lines. The resistors should be placed near the TQ9303. In cases where the line capacitance of the bus traces is less than 3 pF, it may also be necessary to add from 1- 2 pf of capacitance to each trace near the TQ9501. The purpose is to slow the edge rates enough to prevent potential undershoot from disturbing the power supplies in the PLL circuitry of the TQ9501.
Figure 4. Adding resistance and capacitance to the TX data bus.
TQ9301
For additional information and latest specifications, see our website: www.triquint.com
5
DATACOM PRODUCTS
TQ9502 RX
Optical, Coaxial, or Twisted Pair Interface
In
TQ9501/TQ9502
Table 2. Transmitter Pin Descriptions
Symbol
TX, TY TLX, TLY LOOPEN REFCLK
Type
O O I I
Description
Differential Transmitter Outputs connect to an optical transmitter, a coaxial interface or shielded twisted pair interface. LOOPEN low selects TY and TX outputs. LOOPEN high drives TX low and TY high. Loopback Differential Transmitter Outputs connect to the Receiver RLX and RLY inputs. LOOPEN high selects TLY and TLX outputs. LOOPEN low drives TLX low and TLY high. Loopback Enable high selects the TLX and TLY as outputs. LOOPEN low selects the TX and TY as outputs. The PLL multiplies the Reference Clock and generates the high speed clock for transmitting serial data. REFCLK shall be equal to 1/40 of the baud rate. REFCLK shall have a frequency tolerance of 100 ppm to guarantee clock and data recovery on the receiver. The REFCLK operating range is 25 MHz to 31.25 MHz. The ENDEC uses Byte Clock to synchronize to the Transmitter. The ENDEC generates TXCLK from BYTECLK simplifying the synchronization between the Transmitter and ENDEC, as shown on Figure 7. The Transmitter latches the 10 Encoded Data Bits at the rising edge of TXCLK. The Transmitter serially sends TXD9 first and TXD0 last. The Transmitter Data Clock strobes TXD0..9 into the Transmitter. The ENDEC generates TXCLK from BYTECLK simplifying the synchronization between the Transmitter and ENDEC. The Differential Signal Present are inputs to a PECL to TTL translator. The translator is typically used to convert differential signals from a differential optical receiver output to TTL. The TTL equivalent of SIG and SIGN is SIGDET. Signal Detect is the output of the PECL to TTL translator. The translator is typically used to convert differential signals from a differential optical receiver output to TTL. SIGDET is useful when implementing an OFC - Open Fibre Control protocol where the link activity or optical receiver outputs are monitored continuously. Rate Select is used to select between 531 Mbaud (RATESEL=VDD) and 1063 Mbaud (RATESEL=GND) operation.
BYTECLK TXD0..9 TXCLK SIG, SIGN
O I I I
SIGDET
O
RATESEL
I
Figure 5. Fly-By TM Termination Schematic
5V 82 130 5V 82 130 5V 82 130 5V 82 130 RX Z0 = 50 RTX Z0 = 50 RLX Z0 = 50 RLTX Z0 = 50
TQ9502 RX
RLTY RLY
Figure 6. Transmitter Synchronization Ciruit Block Diagram
TQ9303 ENDEC TQ9501 TX
BTXD0..9 TXD0..9 BTXCKOUT
RTY RY
TXCLK BTXCKIN BYTECLK
6
For additional information and latest specifications, see our website: www.triquint.com
TQ9501/TQ9502
Table 3. Receiver Pin Descriptions
Symbol
RX, RY RTX, RTY
Type
I I
Description
The Receiver Differential Inputs connects to an optical, coaxial or shielded twisted pair interface. LOOPEN low selects the RX and RY inputs. LOOPEN high selects the RLX and RLY inputs. The Receiver Differential Termination are used in Fly-ByTM termination. RX is internally connected to RTX and RY is internally connected to RTY. A termination circuit connects to RTX and RTY instead of RX and RY. With Fly-ByTM termination, the termination circuit can be located away from the Receiver instead of requiring termination directly at RX and RY. Both RTX and RTY must be terminated with a 50 chip resistor in series with 3V reference or Thevenin equivalent as shown in Figure 6. The Looped Receiver Differential Inputs connect to the Transmitters TLX and TLY outputs providing a loop back path. LOOPEN high selects the RLX and RLY inputs. LOOPEN low selects the RX and RY inputs. The Receiver Differential Termination are used in Fly-ByTM termination. RLX is internally connected to RLTX and RLY is internally connected to RLTY. A termination circuit connects to RLTX and RLTY instead of RLX and RLY. With Fly-BYTM termination, the termination circuit can be located away from the Receiver instead of requiring termination directly at the RLX and RLY. Both RLTX and RLTY must be terminated with a 50 chip resistor in series with 3V reference or Thevenin equivalent as shown on Figure 6. Loopback Enable high selects the RLX and RLY inputs. LOOPEN low selects the RX and RY inputs. The Reference Clock provides the clock needed by the clock recovery circuit. The REFCLK frequency shall bE chosen to equal 1/40 of the baud rate. REFCLK shall have a frequency tolerance of 100 ppm to guarantee clock and data recovery on the receiver. The receiver automatically locks onto the REFCLK during power-up and/or when no input signals are applied. This prevents the PLL from drifting away from the input data rate. The PLL automatically locks onto the input data stream when it is applied. The frequency range of REFCLK is 25 MHz to 31.25 MHz. When Sync Enable is high, the receiver searches for a K28.5 character from the input data stream and byte aligns the parallel register to this character as defined in the Fibre Channel standard. SYNCEN low disables byte alignment to a K28.5 character and drives SYNC low. The K28.5 character has a pattern of RXD9..0 = 001111 1010 or 110000 0101. Whenever the receiver detects the K28.5 pattern it byte aligns to this character and drives SYNC high for that byte cycle. SYNC is high only in byte cycle where a K28.5 character is present. These are 10 Encoded Data Bits where the first bit received from the serial data stream is RXD9 and the last bit received is RXD0. The receiver generates RXCLK to strobe RXD0..9. If SYNCEN is high, Synchronization to K28.5 goes high for the byte clock cycle in which a K28.5 character is present on the RXD0..9 output. If SYNCEN is low then SYNC is always low. Receiver Data Clock is the strobe for RXD0..9 and SYNC. The phase of RXCLK with respect to RXD0..9 and SYNC changes depending on CLKPOL. CLKPOL high provides a longer setup time and a shorter hold time while CLKPOL low provides a shorter setup time and a longer hold time. The frequency range of RXCLK is 50 MHz to 62.5 MHz in FC531 mode and 100 MHz to 125 MHz in FC1063 mode. Clock Phase or Polarity controls the phase of RXCLK with respect to RXD0..9 and SYNC. CLKPOL high provides a longer setup time and a shorter hold time while CLKPOL low provides a shorter setup time and a longer hold time. Rate Select is used to select between 531 Mbaud (RATESEL=VDD) and 1063 Mbaud (RATESEL=GND) operation.
RLX, RLY
I
RLTX, RLTY
I
LOOPEN REFCLK
I I
SYNCEN
I
RXDO..9 SYNC RXCLK
O O O
CLKPOL
O
RATESEL
I
For additional information and latest specifications, see our website: www.triquint.com
7
DATACOM PRODUCTS
TQ9501/TQ9502
Layout Guidelines
Multiple ground and power pins on the TQ9501/02 reduce ground bounce. Good layout techniques, however, are necessary to guarantee proper operation and to meet the specifications across the full operating range. TriQuint recommends bypassing each of the VDD supply pins to the nearest ground pin, as close to the chip as possible. Figure 7 shows the recommended power layout for the TQ9501/02. The bypass capacitors should be located on the same side of the board as the TQ9501/02. The VDD traces connect to an inner-layer VDD plane. All of the ground pins (GND) are connected to a small ground plane on the surface beneath the chip. Multiple through-holes connect this small surface plane to an inner-layer ground plane. The capacitors are 0.1 F. TriQuint's test board uses X7R temperature-stable capacitors in 1206 SMD cases.
Figure 7. Example Top Layer Layout of Power Pins (Not to scale)
VDD C Pin 1
C VDD
Ground Plane
VDD Rx Only VDD C VDD VDD C C VDD C
Pin 23
Note:
Series resistors and small capacitors may be needed for the TX data bus and clock lines. See the previous "Fibre Channel Interface" section in this datasheet for details.
Table 4. Absolute Maximum Ratings
Parameter
Storage temperature Case temperature Supply voltage to ground DC input voltage DC input current Package Thermal Resistance Die Junction Temperature Note:
Table 5. Operating Conditions
Parameter
Supply voltage Ambient temperature Note:
Range
-65 C to +150 C -55 C to +125 C -0.5 V to +7.0 V -0.5 V to (VDD +0.5 V) 30 mA to +5 mA
jA = 40 C/W; cA = 8 C/W
Tj = 150 C
Range
5V5 0 to 70 C
Proper functionality is guaranteed under these operating conditions.
Stresses above those listed in Absolute Maximum Rating may cause permanent damage to the device. This is a stress-only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied.
Table 6. Test Loads
Symbol
CIN COUT
Description
Input capacitance Output capacitance
Test Conditions
VIN = 2.0 V at f = 1 MHz VOUT = 2.0 V at f = 1 MHz
Min.
Typ.
6 9
Max.
Unit
pF pF
8
For additional information and latest specifications, see our website: www.triquint.com
TQ9501/TQ9502
Table 7. DC Characteristics--TQ9501 Transmitter TTL Signals (TXDO..9, TXCLK, BYTECLK, LOOPEN, SIGDET, REFCLK, RATESEL) (Over operating range unless otherwise specified)
Symbol
VOH VOL ISC4 IIL IIH II VIH5 VIL5 VI IDD
Description
Output HIGH voltage Output LOW voltage Output short-circuit current Input LOW current Input HIGH current Input HIGH current Input HIGH level Input LOW level Input clamp voltage Power supply current
Test Conditions
VDD = Min VIN2 = VIH or VIL VDD = Min VIN2 = VIH or VIL VDD = Max VDD = Max VDD = Max VDD = Max IOH = -1.6 mA IOH = -3.2 mA3 IOL = 4 mA IOL = 8 mA3 VOUT = 0.5 V VIN = 0.4 V VIN = 2.7 V VIN = 5.5 V
Min.
2.4
Limits 1 Typ.
3.2 0.2
Max.
Unit
V
0.5 -120 - 400 25 1
V mA A A mA V
-15
Guaranteed input logical HIGH voltage for all inputs, VDD = Max Guaranteed input logical LOW voltage for all inputs VDD = Min VDD = Max, static IIN = -18 mA
2.0 0.8 -1.2 175 220
V mA
Table 8. DC Characteristics--TQ9501 Transmitter PECL Signals (TX, TY, TLX, TLY, SIG, SIGN)
Limits 1 Typ.
Symbol
VOH VOL VCMO DVOUT IIL IIH VIHS VILS VDIF VICM
Description
Output HIGH voltage Output LOW voltage Output common mode voltage Output differential voltage Input LOW current Input HIGH current Highest input HIGH voltage Lowest input LOW voltage Differential input voltage Input common mode voltage
Test Conditions
VDD = Min PECL load VDD = Min PECL load
Min.
VDD - 1.200 VDD - 2.00 VDD - 1.60 0.60
Max.
VDD - 0.50 VDD - 1.60 VDD -1.10 1.2 200 250 VDD - 0.5
Unit
V V V V A A V V V V
VDD = Max VDD = Max VDD = Min VDD = Max VDD = Min VDD = Min
VIN =2.4 V VIN = VDD - 0.5 V 2.4 0.4 2.8
1.2 VDD - 0.7
Notes: 1. Typical limits are: VDD = 5.0 V and TA = 25 C. 2. The TTL inputs could be HIGH or LOW. 3. The IOL and IOH specifications are valid only for the BYTECLK. 4. These are absolute values with respect to device ground. 5. No more than one output should be tested at a time. Duration of the short circuit should not exceed one second.
For additional information and latest specifications, see our website: www.triquint.com
9
DATACOM PRODUCTS
V
TQ9501/TQ9502
Table 9. DC Characteristics--TQ9502 Receiver TTL Signals (RXD0..9, RXCLK, SYNCEN, REFCLK, LOOPEN, SYNC, CLKPOL, RATESEL) (Over operating range unless otherwise specified)
Symbol
VOH VOL ISC5 IIL IIH II VIH4 VIL4 VI IDD
Description
Output HIGH voltage Output LOW voltage VIN2 = VIH or VIL Output short-circuit current Input LOW current Input HIGH current Input HIGH current Input HIGH level voltage for all inputs Input LOW level voltage for all inputs Input clamp voltage Power supply current
Test Conditions
VDD = Min VIN2 = VIH or VIL IOH = -1.6 mA = -3.2 mA3
Min.
2.4 0.2
Limits 1 Typ.
3.2 0.5
Max.
Unit
V
VDD = Min IOL = 4 mA = 8 mA3 VDD = Max VDD = Max VDD = Max VDD = Max VOUT = 0.5 V VIN = 0.40 V VIN = 2.7 V VIN = 5.5 V
V -120 -400 25 1 mA A A mA V 0.8 -1.2 V V mA
-15
Guaranteed input logical HIGH Guaranteed input logical LOW VDD = Min VDD = Max, static IIN = -18 mA
2.0
280
350
Table 10. DC Characteristics--TQ9502 Receiver PECL Signals (RX, RY, RTX, RTY, RLX, RLY, RLTX, RLTY)
Limits 1 Typ.
Symbol
IIL IIH VIHS VILS VDIF VICM
Description
Input LOW current Input HIGH current Highest input HIGH voltage Lowest input LOW voltage Differential input voltage Input common mode voltage
Test Conditions
VDD = Max VDD = Max VDD = Max VDD = Min VDD = Min VDD = Min VIN = 2.4 V VIN = VDD -0.5 V
Min.
0.5
Max.
200 250 VDD - 0.50
Unit
A A V V V V
2.4 0.4 2.8 1.2 VDD - 0.7
Notes:
1. Typical limits are: VDD = 5.0 V and TA = 25 C. 2. The TTL inputs could be HIGH or LOW. 3. The IOL and IOH specifications are valid only for the RXCLK. 4. These are absolute values with respect to device ground. 5. No more than one output should be tested at a time. Duration of the short circuit should not exceed one second.
10
For additional information and latest specifications, see our website: www.triquint.com
TQ9501/TQ9502
Table 12. AC Specifications--TQ9501 Transmitter Parameters with dual values refer to 531Mbaud/1063Mbaud operation respectively.
Parameter
T1 T2 T31 T4 T5 T6 T7 T8 T9 T10 T11 T123
Description
REFCLK pulse width HIGH REFCLK pulse width LOW REFCLK period (T) TXD 9..0 setup time TXD 9..0 hold time BYTECLK, TXCLK pulse width HIGH BYTECLK, TXCLK pulse width LOW BYTECLK, TXCLK period (T) TX, TY, TLX, TLY rise time TX, TY, TLX, TLY fall time TX ~ TY or TLX ~ TLY skew
Min.
10.0 10.0 32.0 2.0 2.0 6.0/3.0 6.0/3.0 16.0/8.0 100 100
Typ.
Max.
Units
ns ns
40.0
ns ns ns ns ns
20.0/10.0 400/300 400/300 100/60 100/75 200/150
ns ps ps ps ps ps
TX , TY or TLX , TLY output jitter - deterministic jitter (DJ) - random jitter (RJ)
Notes: 1. REFCLK Tolerance = (20/baud rate) 0.01%, for baud rate of 500Mbaud to 625Mbaud and (40/baud rate) 0.01%, for baud rate of 1 Gbaud to 1.25 Gbaud. 2. baud time = 1/baud rate 3. The jitter numbers are for a BER of 10-12.
Figure 8. Bus Timing - TQ9501 Transmitter
REFCLK T1 T3 TXD0..9 T4 TXCLK BYTECLK T6 T8 T7 T5 T2
Figure 9.Serial Output Timing - TQ9501
T12 TX, TLX T9 T12 T11 T10 80% 50% 20%
TY, TLY T12 T12
50%
For additional information and latest specifications, see our website: www.triquint.com
11
DATACOM PRODUCTS
TQ9501/TQ9502
Table 12. AC Specifications--TQ9502 Receiver Parameters with dual values refer to 531Mbaud/1063Mbaud operation respectively.
Parameter
T21 T22 T231 T24 T25 T261 T271 T281 T29 T30 T31 T32
Description
REFCLK pulse width LOW REFCLK pulse width HIGH REFCLK period Setup Time RXD 0..9 & SYNC Hold Time RXD 0..9 & SYNC RXCLK period RXCLK pulse width HIGH RXCLK pulse width LOW RX, RY, RLX, RLY rise time RX, RY, RLX, RLY fall time RX ~ RY, RLX ~ RLY skew RX, RY, RLX, RLY peak-to-peak input jitter 32.0 CLKPOL=0 CLKPOL=1 CLKPOL=0 CLKPOL=1
Min.
10.0 10.0
Typ.
Max.
Units
ns ns
40.0 4.0/2.0 12.0/6.0 8.0/4.0 0 16.0/8.0 6.0/4.0 6.0/4.0
ns ns ns ns ns 20.0/10.0 ns ns ns 0.4 baud time 0.4 baud time 0.3 baud time 0.7 baud time ns ns ns ns
Notes:
1. REFCLK Tolerance = (20/baud rate) 0.01%, for baud rate of 500Mbaud to 625Mbaud and (40/baud rate) 0.01%, for baud rate of 1 Gbaud to 1.25 Gbaud. 2. baud time = 1/baud Rate 3. The jitter numbers are for a BER of 10-12.
Table 13. Synchronization Times
Description
Power Up or application of REFCLK to receiver synchronization Application of valid data to receiver synchronization Receiver resynchronization after phase shift on data
Min.
Typ.
Max.
1 200 2500
Units
ms s bit time
Figure 10. Bus Timing - TQ9502 Receiver
T21 REFCLK T23 T24 RXD0..9 SYNC T26 RXCLK T27 T28 T25 T22
12
For additional information and latest specifications, see our website: www.triquint.com
TQ9501/TQ9502
Figure 11. Serial Input Timing - TQ9502
RX, RTX, RLX, RLTX T29 T30 T31
80% 50% 20%
RY, RTY, RLY, RLTY T32 T32
50%
Figure 12a. TTL Test Load,RXCLK
DATACOM PRODUCTS
VDD
1000
Figure 12b. TTL Test Load, All Other TLL Outputs
680
VDD
2000
1370
Figure 12c. PECL Test Load
VDD
82
130
For additional information and latest specifications, see our website: www.triquint.com
13
TQ9501/TQ9502
Figure 13. Pinout for Transmitter
TXD3 TXD4 TXD5 TXD6 TXD7 TXD8 TXD9 GND VDD NC NC
6
5
4
3
2
GND TXD2 TXD1 TXD0 NC NC NC SIG NC SIGN VDD
7 8 9 10 11 12 13 14 15 16
1 44 43 42 41 40 39 38 37 36
VDD SIGDET BYTECLK RATESEL VDD TXCLK GND REFCLK VDD LOOPEN VDD
Tx TQ9501
35 34 33 32 31 30
29 17 18 19 20 21 22 23 24 25 26 27 28
GND
GND
Table 14. Pin Definitions - TQ9501 Transmitter
Symbol
TX, TY TLX, TLY SIG, SIGN TXCLK TXD 0..9 LOOPEN SIGDET REFCLK BYTECLK VDD GND NC RATESEL
Pin #
20, 21 25, 26 14, 16 34 10, 9, 8, 5, 4, 2, 1, 44, 42, 41 30 38 32 37 6, 17, 29, 31, 35, 39 7,18, 23, 28, 33, 40 3,11, 12, 13, 15, 19, 22, 24, 27, 43 36
I/O
Output Output Input Input Input Input Output Input Output -- -- -- Input
# Pins
2 2 2 1 10 1 1 1 1 6 6 10 1
Logic Type
PECL PECL PECL TTL TTL TTL TTL TTL TTL -- -- -- --
Active
NRZ NRZ HIGH HIGH HIGH HIGH HIGH HIGH HIGH -- -- -- --
GND
NC
TX
TY
NC
NC
TLX
TLY
NC
Description
Differential serial data output Loopback differential serial data output Differential optical signal present Transmit clock Transmit data input Enable loopback Signal detect Oscillator clock (25 to 31.25 MHz) Byte clock +5 Volt Supply Ground No Connect VDD (1) for 531Mbaud operation Ground (0) for 1063Mbaud operation
14
For additional information and latest specifications, see our website: www.triquint.com
TQ9501/TQ9502
Figure 14. Pinout for Receiver
RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 GND GND VDD VDD
6
5
4
3
2
GND RXDO RXCLK RATESEL GND SYNCEN VDD REFCLK GND LOOPEN VDD
7 8 9 10 11 12 13 14 15 16
1 44 43 42 41 40 39 38 37 36
VDD RXD8 RXD9 SYNC VDD CLKPOL GND NC VDD NC VDD
Rx TQ9502
35 34 33 32 31 30
Table 15. Pin Definitions - TQ9502 Receiver
Symbol
RX, RY RLX, RLY RTX, RTY RLTX, RLTY RXD 0..9 RXCLK REFCLK SYNC SYNCEN LOOPEN CLKPOL VDD GND NC RATESEL
Pin #
26, 25 21, 20 27, 24 22, 19 8, 5, 4, 2, 1, 44, 42, 41, 38, 37 9 14 36 12 16 34 6, 13, 17, 29, 31, 35, 39, 43 3, 7, 11, 15, 18, 23, 28, 33, 40 30, 32 10
I/O
I I I I O O I O I I I -- -- -- I
# Pins
2 2 2 2 10 1 1 1 1 1 1 8 9 2 1
Logic Type
PECL PECL PECL PECL TTL TTL TTL TTL TTL TTL TTL -- -- -- --
Active
NRZ NRZ NRZ NRZ HIGH HIGH HIGH HIGH HIGH HIGH LOW -- -- -- --
Description
Differential serial data input Differential serial data input, loopback For fly-by termination For fly-by termination Receive output data Receive clock Oscillator clock (25 MHz to 31.25 MHz) Receive byte sync Sync Enable or Align to K28.5 Enable loopback RXCLK Clock Phase +5 V supply Ground No connect VDD(1) for 531Mbaud operation Ground(0) for 1063 Mbaud operation
For additional information and latest specifications, see our website: www.triquint.com
15
DATACOM PRODUCTS
29 17 18 19 20 21 22 23 24 25 26 27 28
GND
GND
RY
RX
RLTY
RLTX
GND
RLY
RLX
RTY
RTX
TQ9501/TQ9502
Figure 15. 44-Pin MQuad J-leaded Package
.690 .005 .045 X 45 .645
.172 .0125 .104 .01 .030 .01
PIN 1 .018 .004
12 0.125 VENT PLUG
34
.645 .690 .005 .028
.050 TYP
.610 .015
23 .015 X 45 .050 BSC .132
Ordering Information
TQ9501-MC TQ9502-MC
Additional Information
FC531/1063 Transmitter FC531/1063 Receiver
For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: sales@tqs.com Tel: (503) 615-9000 Fax: (503) 615-8900
For technical questions and additional information on specific applications: Email: applications@tqs.com
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright (c) 1997 TriQuint Semiconductor, Inc. All rights reserved. Revision 1.1.A November 1997
16
For additional information and latest specifications, see our website: www.triquint.com

▲Up To Search▲

Price & Availability of TQ9501

	To Download TQ9501 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .